The present invention relates to a phase change memory device, and more particularly to a phase change memory device in which a carbon nano tube is applied as a lower electrode material, and a manufacturing method thereof.
Memory devices are largely divided into Random Access Memory (RAM) and Read Only Memory (ROM) devices. Whereas a RAM device is a volatile memory device that loses input information if power is shut off, the ROM device is a non-volatile memory device that preserves the stored state of input information even in the event of a power shut off. Examples of the volatile RAM device include Dynamic Random Access memory (DRAM) devices and Static Random Access memory (SRAM) devices, and examples of the non-volatile ROM device include flash memory devices such as Electrically Erasable and Programmable ROM (EEPROM) devices.
It is well known in the art that although the DRAM device is a very good memory device, it is difficult to highly integrate because it requires a high charge storage capacity, thus requiring its electrode surface area to be increased. Further, it is also difficult to highly integrate the flash memory device because its laminated structure of two gates requires an operation voltage higher than a power source voltage, which necessitates a separate booster circuit to establish a voltage necessary for write and erase operations.
Thereupon, many studies are being pursued to develop new non-volatile memory devices with a simple structure that can be highly integrated. As an example of such memory devices, a phase change memory (in particular, phase change RAM) has recently been proposed.
The phase change memory device is a memory device in which the current flow between upper and lower electrodes causes the phase change layer interposed between the electrodes to undergo a phase change from a crystalline phase to an amorphous phase. The types of information stored in the memory cell are then discerned using the resistance difference according to the phase change of the phase change layer. More specifically, the phase change memory device uses a Chalcogenide layer, that is, a compound layer of Germanium (Ge), Stibium (Sb) and Tellurium (Te), as a phase change layer. Heat generated through the application of a current, that is, so-called Joule heat, causes the Chalcogenide layer to undergo a phase change between a crystalline phase and an amorphous phase. Here, because the phase change layer has a higher resistance when in the amorphous phase as compared to the crystalline phase, the phase change memory device determines whether information stored in a phase change memory cell corresponds to logic “1” or logic “0” by detecting the current flowing through the phase change layer in a read mode.
In such a phase change memory device, the crystalline-to-amorphous phase change of the phase change layer is referred to as “reset” while the amorphous-to-crystalline phase change of the phase change layer is referred to as “set”. In view of current consumption and operation speed, it is optimal for the magnitude of a current inducing the reset/set (programming) to be as low as possible. Thus, the current required for the phase change must be lowered by minimizing the contact area between the phase change layer and the lower electrode. In order to do so, the lower electrode is conventionally formed in the shape of a plug while its diameter is reduced as much as possible.
However, when a nitride-based metal layer, such as a TiN, is formed as a plug-shaped lower electrode with a diameter of below 40 nm, it cannot endure a high-current density (about 108A/cm2) at a narrow contact interface, thereby leading to the deterioration of its characteristics.
Thus, a material referred to as carbon nano tube, which has a hollow rod-like structure and excellent electrical conductivity properties, has been proposed as a new lower electrode material and is being vigorously researched.
The carbon nano tube has not only the electrical conductivity of several hundred times that of copper but also the thermal conductivity of fifteen times that of copper. Furthermore, the carbon nano tube never causes surface scattering or grain boundary scattering. Therefore, by applying the carbon nano tube as a plug-shaped lower electrode material, it is possible to create a phase change memory device that has high operation speed and low power consumption without risking deterioration of its characteristics even at a narrow contact interface with a diameter of below 40 nm.
A conventional phase change memory device in which a carbon nano tube is applied as a lower electrode material may be manufactured as follows.
A first contact hole is formed in the first insulating interlayer, and a contact plug is formed within the first contact hole. By using a damascene process, an insulating layer and an electrically conductive pattern contacting the contact plug are formed on the first insulating interlayer including the contact plug. A second insulating interlayer is formed on the insulating layer including the electrically conductive pattern, and a second contact hole, through which the electrically conductive pattern is exposed, is formed in the second insulating interlayer. A carbon nano tube is grown within the second contact hole by using the electrically conductive pattern as a catalytic agent. In this way, a carbon nano tube lower electrode is formed. A phase change layer and an upper electrode are formed in sequence on the carbon nano tube lower electrode and the second insulating interlayer portion adjacent thereto.
The electrically conductive pattern is formed using a damascene process, and it subsequently functions as a catalytic agent for the growth of the carbon nano tube. The electrically conductive pattern is formed using a damascene process to ensure the uniformity of the thickness of the second insulating interlayer. If the electrically conductive pattern is instead formed using a common patterning method, the insulating layer is formed on the first insulating interlayer in such a manner so as to cover the electrically conductive pattern, thus requiring the planarization of the surface of the insulating layer by means of a Chemical mechanical Polishing (CMP) process. However, since the polishing speed of the CMP process differentiates from place to place of a wafer, it is difficult to ensure the uniformity of the insulating interlayer's thickness, and thus the contact hole for the lower electrode cannot be formed with a uniform size, resulting in uneven device characteristics. The electrically conductive pattern is therefore formed using a damascene process.
As stated above, in view of the superior current density endurance of the carbon nano tube, a phase change memory device with low power consumption and high operation speed can be manufactured when the carbon nano tube is applied as a lower electrode material.
However, in the above-mentioned prior art, the need to separately form the insulating layer and the electrically conductive pattern leads to an increase in the overall height of the device and creates difficulties in the manufacturing process. Furthermore, the use of a damascene process to form the electrically conductive pattern and the insulating layer in order to ensure the uniformity of the thickness of the second insulating layer, also burdens the manufacturing process.